1. Technical Field of the Invention
The present invention relates to a semiconductor memory device that is provided with a data compressing circuit that compresses and outputs read data, and shortens the time for testing.
2. Background Art
In order to shorten the testing time when testing semiconductor memory devices, it has been the conventional practice to simultaneously test several devices using an LSI tester. The number of measurement terminals on the LSI tester used in the test is limited, however. Accordingly, the number of semiconductor memory devices that can be simultaneously tested has been restricted based on the number of output terminals possessed by the semiconductor memory device.
For example, in the case of a semiconductor memory device having an 8 bit output terminal number, only 8 devices can be tested simultaneously in an LSI tester capable of simultaneously testing 64 terminals.
Similarly, in the case of a semiconductor memory device having a 16 bit output terminal number, only 4 devices can be tested simultaneously in an LSI tester capable of simultaneously testing 64 terminals.
At present, the bit number for data processing in microcomputers and the like is rising, however, so that an increase in the output terminal number beyond those cited above can be anticipated.
At the same time, advances in process technologies in the field of semiconductor manufacturing have led to an increase in the memory capacity per semiconductor memory device.
In particular, the holding characteristics for the charge held in the memory capacitor must be tested in the dynamic random access memory (DRAM). In this test, data is written into the memory cell, read out several seconds later for example, and a judgment is made as to whether or not the read out information is the same as the write information. Because this test is carried out for each semiconductor memory device, or for each memory cell, it requires several hours.
Thus, when the semiconductor memory device has an output terminal number of 64, the number of semiconductor memory devices which can be tested each time is just one in the case where using a LSI tester capable of simultaneously testing 64 terminals. While increasing the number of measurement terminals which can be tested simultaneously in the LSI tester might be considered, it becomes an extremely expensive capital investment in order to carry out high accuracy testing of properties at high speed.
Moreover, since it is not clear how many output terminals will be in future generations of semiconductor memory devices, it is impossible to determine how far the test bit number needs to be increased.
When testing a semiconductor memory device, a data compressing test mode is employed as a method for performing multiple bit testing simultaneously with a limited output terminal number. Namely, in a semiconductor memory device having a 16 bit output terminal number, 16 bit data is data compressed to 2 bits, and output from two output terminals. As a result, an LSI tester capable of simultaneously testing 64 terminals can test 32 semiconductor memory devices simultaneously without changing the testing time for each unit.
In a semiconductor memory device in which data from one or two input terminals typically determined in advance is input, if there is an input/output terminal number for the data in the semiconductor memory devicexe2x80x94for example, 16 input/output terminals for a 16 bit data portionxe2x80x94then the same data is written in the memory cells for each 16 bits. When reading out the data stored in the memory cell, the 16 bit data values are compressed, and the value of the compressed result is used to determine whether or not the data is accurately stored in the memory cell. The above-described testing method is referred to a xe2x80x9cparallel testingxe2x80x9d.
For example, the means for carrying out the aforementioned data compression will be explained using FIGS. 8, 9, and 10. FIGS. 8 and 9 are block diagrams showing the structure of data compressing circuit 100 in a semiconductor memory device having a conventional 16 bit (i.e., data terminal TD0xcx9cdata terminal TD15) output terminal. FIG. 10 is a schematic diagram showing the structure of a semiconductor memory device (DRAM: dynamic random access memory) in which the data compressing circuit shown in FIGS. 8 and 9 is installed.
In FIG. 10, the memory cell domain is divided into four domains, i.e., memory bank BANK100xcx9cmemory bank BANK103. Each of the memory banks is formed of four blocks. Memory bank BANK100xcx9cmemory bank BANK103 are formed in the same manner, and the operation enable state is selected according to an address signal input from an external device.
For this reason, memory bank BANK100 will be explained in detail as a representative example of memory bank BANK100xcx9cmemory bank BANK103. Structural components in the other memory banks which are identical to the structures in memory bank BANK100 will be assigned the same numeric symbol and an explanation thereof will be omitted.
Memory bank BANK100 is formed of memory block MB100xcx9cmemory bank MB103. X decoder XDEC100 activates a specific word line based on an address signal input from an external device. Y decoder YDEC100 activates a column switch (Y switch) which connects a specific bit line to a global I/O line based on the address signal input from the external device.
Four global I/O lines GIO100xcx9cGIO103 (corresponding to data terminal TD0xcx9cdata terminal TD3, respectively) are provided to memory block MB100. Data amp DAP100xcx9cdata amp DAP103 are connected to global I/O line GIO100xcx9cglobal I/O line GIO103, respectively. Data amp DAP100xcx9cdata amp DAP103 increase the voltage of the data in the bit line selected by the column switch when reading out the data recorded in the memory cell of the semiconductor memory device during data read out.
Similarly, global I/O line GIO104xcx9cglobal I/O line GIO107 (corresponding to data terminal TD4xcx9cdata terminal TD7), global I/O line GIO108xcx9cglobal I/O line GIO111 (corresponding to data terminal TD8xcx9cdata terminal TD11), and global I/O line GIO112xcx9cglobal I/O line GIO115 (corresponding to data terminal TD12xcx9cdata terminal TD15) are provided to memory block MB101xcx9cmemory block MB103, respectively.
Global I/O line GIO104xcx9cglobal I/O line GIO107, global I/O line GIO108xcx9cglobal I/O line GIO111, and global I/O line GIO112xcx9cglobal I/O line GIO115, are connected to data amp DAP104xcx9cdata amp DAP107, data amp DAP108xcx9cdata amp DAP111, and data amp DAP112xcx9cdata amp DAP115, respectively.
For example, a specific memory cell in the memory block MB100 shown in FIG. 10 is selected by activating the word line corresponding to X decoder XDEC100 and the column switch corresponding to Y decoder 100, and the voltages of the data recorded in each of the memory cells is read out to global I/O line GIO100xcx9cglobal I/O line GIO103.
Data amp DAP100xcx9cdata amp DAP103 amplify the voltage corresponding to the data read out from each global I/O line GIO100xcx9cglobal I/O line GIO103 (corresponding to data terminal TD0xcx9cdata terminal TD3). As a result, data amp DAP100 outputs data signal RWBST100 and data signal RWBSN100, which is the inversion of data signal RWBST100, to line LT100 and line LN100, respectively.
Data amp DAP101xcx9cdata amp DAP103 output data signal RWBST101xcx9cdata signal RWBST103 and data signal RWBSN101xcx9cdata signal RWBSN103, obtained by inverting data signal RWBST101xcx9cdata signal RWBST103, to line LT101xcx9cline LT103 and line LN101xcx9cline LN103.
A specific memory cell in memory block MB101 is selected by activating the word line corresponding to X decoder XDEC100 and the column switch corresponding to Y decoder 100, and the voltages of the data recorded in each of the memory cells are read out to global I/O line GIO104xcx9cglobal I/O line GIO107, respectively.
Data amp DAP104xcx9cdata amp DAP107 amplify the voltages corresponding to the data read out from each global I/O line GIO 104xcx9cglobal I/O line GIO107 (corresponding to each data terminal TD4xcx9cdata terminal TD7, respectively). As a result, data amp DAP104 outputs data signal RWBST104 and data signal RWBSN104, which is the inversion of data signal RWBST104, to line LT104 and line LN104, respectively.
Data amp DAP105xcx9cdata amp DAP107 output data signal RWBST105xcx9cdata signal RWBST107 and data signal RWBSN105xcx9cdata signal RWBSN107, which is the inversion of data signal RWBST105xcx9cdata signal RWBST107, to each line LT105xcx9cline LT107 and line LN105xcx9cline LN107, respectively.
A specific memory cell in memory block MB102 is selected by activating the word line corresponding to X decoder XDEC100 and the column switch corresponding to Y decoder 100, and the voltages of the data recorded in each of the memory cells is read out to global I/O line GIO108xcx9cglobal I/O line GIO111, respectively.
Data amp DAP108xcx9cdata amp DAP111 amplify the voltages corresponding to the data read out from each global I/O line GIO 108xcx9cglobal I/O line GIO111 (corresponding to each data terminal TD8xcx9cdata terminal TD11). As a result, data amp DAP108 outputs data signal RWBST108 and data signal RWBSN108, which is the inversion of data signal RWBST108, to line LT108 and fine LN108, respectively.
Data amp DAP109xcx9cdata amp DAP111 output data signal RWBST109xcx9cdata signal RWBST111 and data signal RWBSN109xcx9cdata signal RWBSN111, which is the inversion of data signal RWBST109xcx9cdata signal RWBST111, to each line LT109xcx9cline LT111 and line LN109xcx9cline LN111, respectively.
A specific memory cell in memory block MB103 is selected by activating the word line corresponding to X decoder XDEC100 and the column switch corresponding to Y decoder 100, and the voltages of the data recorded in each of the memory cells is read out to global I/O line GO112xcx9cglobal I/O line GIO115, respectively.
Data amp DAP112xcx9cdata amp DAP115 amplify the voltages corresponding to the data read out from each global I/O line GIO112xcx9cglobal I/O line GIO115 (corresponding to each data terminal TD12xcx9cdata terminal TD15). As a result, data amp DAP112 outputs data signal RWBST112 and data signal RWBSN112, which is the inversion of data signal RWBST112, to line LT112 and line LN112, respectively.
Data amp DAP113xcx9cdata amp DAP115 output data signal RWBST113xcx9cdata signal RWBST115 and data signal RWBSN113xcx9cRWBSN115, obtained by inverting data signal RWBST113xcx9cRWBST115, to each line LT113xcx9cline LT115 and line LN113xcx9cline LN115, respectively.
As explained above, the data stored in each memory cell in memory bank BANK100 is output to line LT100xcx9cline LT115 and line LN100xcx9cline LN115 as data signal RWBST100xcx9cdata signal RWBST115 and data signal RWBSN100xcx9cdata signal RWBSN115.
In the same manner as memory bank BANK100, memory bank BANK101xcx9cmemory bank BANK103 designate the data stored in each of the memory cells as data signal RWBST100xcx9cdata signal RWBST115 and data signal RWBSN100xcx9cdata signal RWBSN115, which are the inverse of data signal RWBST100xcx9cdata signal RWBST115, in accordance with the external address, and relay these data to line LT100xcx9cline LT115 and line LN100xcx9cline LN115.
As a result, the data compressing circuit 100 shown in FIGS. 8 and 9 compresses data signal RWBST100xcx9cdata signal RWBST115 and data signal RWBSN100xcx9cdata signal RWBSN115, which are input via line LT100xcx9cline LT115 and line LN100xcx9cline LN115, respectively, and output from data amp DAP100xcx9cdata amp DAP115, respectively.
A determination is then made as to whether or not the data in each memory cell of memory bank BANK100xcx9cmemory bank BANK103 is correctly stored based on the compressed data that is output as a result of the compression operation.
This determination operation for the stored data in the memory cell will now be explained in detail using FIG. 8.
Data compressing circuit 100 shown in FIGS. 8 and 9 compresses to 1 bit the 8 bit data of data signal RWBST100xcx9cdata signal RWBST107 and data signal RWBSN100xcx9cdata signal RWBSN107, which were output from each data amp DAP100xcx9cdata amp DAP107 in memory bank 100xcx9cmemory bank BANK103. The data which is the 1 bit portion is indicated here using RWBST100 and RWBSN100.
Similarly, data compressing circuit 100 compresses to 1 bit the 8 bit data of data signal RWBST108xcx9cdata signal RWBST115 and data signal RWBSN108xcx9cdata signal RWBSN115 which was output from each data amp DAP108xcx9cdata amp DAP115 in memory bank 100xcx9cmemory bank BANK103.
For example, control signal RST is input to terminal T101 at [H], latch LTH100 is reset, and the output from output terminal Q of latch LTH100 becomes [L]. Here, at latch LTH100, when [H] is input to control terminal S, then [H] is output to output terminal Q, while when [H] is input to control terminal R, [L] is output to output terminal Q.
Control signal PTEST is input to terminal T100 at [H], and the semiconductor memory device enters the parallel testing state. In this case, [H] data is written in all of the memory cells.
An address signal is input from an external device, and each data signal RWBST100xcx9cdata signal RWBST115 and data signal RWBSN100xcx9cdata signal RWBSN115 are output by data amp DAP100xcx9cdata amp DAP115.
The compression process and the determination of the results are equivalent in the case of data signal RWBST100xcx9cdata signal RWBST107 and data signal RWBSN100xcx9cdata signal RWBSN107, and data signal RWBST108xcx9cdata signal RWBST115 and data signal RWBSN108xcx9cdata signal RWBSN115. Accordingly, an explanation will be made of data signal RWBST100xcx9cdata signal RWBST107 and data signal RWBSN100xcx9cdata signal RWBSN107 compression processing and result determination.
Data stored in the memory cell selected by the address signal is read out. In the result of this read out, all data signal RWBST100xcx9cdata signal RWBST107 are [H] and all data signal RWBSN100xcx9cdata signal RWBSN107 are [L].
As a result, the respective outputs of NAND circuit NAND100, NAND circuit NAND103 and NAND circuit NAND106 are [L].
Conversely, the respective outputs of NAND circuit NAND101, NAND circuit NAND104 and NAND circuit NAND107 are [H].
As a result, the output of NAND circuit NAND102, NAND circuit NAND105 and NAND circuit NAND108 becomes [H]. As a result, the output of NAND circuit NAND109 becomes [L]. Accordingly, the result of the determination of the data output from the memory cell is xe2x80x9cgood qualityxe2x80x9d without there being a change in the output of LATCH LTH100.
Data stored in the memory cell selected by the address signal is read out, and in the read out result, all data signal RWBST100xcx9c107 are [L] and all data signal RWBSN100xcx9c107 are [H].
As a result, the respective outputs of NAND circuit NAND100, NAND circuit NAND 103 and NAND circuit NAND106 is [H].
Conversely, the respective outputs of NAND circuit NAND101, NAND circuit NAND104 and NAND circuit NAND107 becomes [L].
As a result, the output of NAND circuit NAND102, NAND circuit NAND105 and NAND circuit NAND108 becomes [H]. As a result, the output of NAND circuit NAND109 becomes [L]. Accordingly, the result of the determination of the data output from the memory cell is xe2x80x9cgood qualityxe2x80x9d without there being a change in the output of LATCH LTH100.
Next, the data stored in the memory cell selected by the address signal is read out. In the read out result, all the data signals RWBST100xcx9cRWBST106 and data signal RWBST107 are [L], and all the data signals RWBSN100xcx9cRWBSN106 and data signal RWBST 107 are [H].
As a result, the respective outputs of NAND circuit NAND100, NAND circuit NAND103, NAND circuit NAND106, and NAND circuit NAND107 become [H].
Further, the respective outputs of NAND circuit NAND101, NAND circuit NAND104 and NAND circuit NAND107 become [L].
As a result, the output of NAND circuit NAND102, NAND circuit NAND105 becomes [H], and the output of the NAND circuit NAND108 becomes [L]. Therefore, the output of NAND circuit NAND109 becomes [H]. Accordingly, the output of latch LTH100 changes from [L] to [H], and the result of the determination of the data output from the memory cells is xe2x80x9cpoor qualityxe2x80x9d.
Similarly, the data compression of data signal RWBST108xcx9cdata signal RWBST115 and data signal RWBSN108xcx9cdata signal RWBSN115 is carried out by NAND circuit NAND111xcx9cNAND circuit NAND120. The results of the determination are output from the output terminal Q of latch LTH101.
As a result of the above-described parallel testing, the determination of the quality of the memory cell is made after compressing 8 bits of data to 1 bit. Thus, a quality determination test can be carried out for a semiconductor memory device having a 16 bit output terminal using a 2 bit input terminal. In a LSI tester capable of simultaneously testing 64 bits, it is possible to carry out a determination of the quality of 32 semiconductor memory devices simultaneously.
The voltage of the power source required for operation in the conventional semiconductor memory device is a high 5V. For this reason, when a data signal having a 5V power source voltage amplitude is transmitted across the long distance from the sense amp vicinity to the output terminal vicinity, the signal waveform becomes looser and the delay time in the data signal becomes larger.
Increasing the drive capacity of the data amp may be considered as a strategy for reducing this delay time. However, the chip size of the semiconductor memory device increases as a result, while the electrical current consumed during operation increases. Accordingly, this is not a desirable counterstrategy.
For this reason, in the conventional semiconductor memory device, the amplitude of the output signal is reduced and two signal lines are used for 1 bit. A positive phase data signal is supplied to one signal line, while a complementary data signal is supplied to the other signal line. The output buffer disposed near the vicinity of the output terminal converts the small amplitude signal to a 5V amplitude signal, and outputs it to an external device.
Here, even if the transmission of the data signal is carried out at a small amplitude, a determination of the original data signal can be made by comparing the voltage levels of the positive phase and complementary signal lines. Thus, it becomes possible to output the data signal to the external device as a 5V amplitude signal. In the conventional device, the above-described processing was carried out, so that higher speed and lower power consumption could be anticipated.
However, the above-described semiconductor memory device requires a complementary signal for the 1 bit that is output by the data compressing circuit shown in FIGS. 8 and 9 from the output terminal. Thus, 2 lines are necessary per output terminal.
In other words, the data compressing circuit shown in FIGS. 8 and 9 compresses 16 bits of data to 2 bits. Thus, this semiconductor memory device requires data signal RWBST00xcx9cdata signal RWBST115 and data signal RWBSN100xcx9cdata signal RWBSN115.
Thus, it is necessary in the above-described semiconductor memory device to form 32 lines LT100xcx9cLT115 and LN100xcx9cLN115, in order to output data signal RWBST100xcx9cdata signal RWBST115 and data signal RWBSN100xcx9cdata signal RWBSN115 to the data compressing circuit from each data amp DAP100xcx9cdata amp DAP115 of memory bank BANK100xcx9cmemory bank BANK103 as shown in FIG. 10.
As a result, the conventional semiconductor memory device having a data compressing circuit requires 32 lines, i.e., two times more lines than the number of output terminals. For this reason, the chip area in the semiconductor memory device increases due to the formation of these lines. Moreover, given that a further increase in the output terminal number may be anticipated, the semiconductor memory device employing a data compressing circuit of the conventional type will require more area for forming these lines.
The conventional data compressing circuit includes logic for performing compression using two signals, including a complementary signal, for one bit of data. Since a large gate number is required, the scale of the circuit becomes larger, and the chip area in the semiconductor memory device increases due to the circuit design. Moreover, since the output terminal number is expected to increase, a semiconductor memory device employing a data compressing circuit of the conventional type will have to increase the number of gates used in the compression logic accompanying the increase in the output terminal number. Thus, extra area for forming the data compressing circuit will be needed.
The present invention was conceived in view of the above described circumstances, and has as its objective the provision of a semiconductor memory device in which the number of signal lines necessary for the data compressing circuit can be reduced, the area for forming the signal lines can be decreased, the circuit design is simple and the area for forming the data compressing circuit can be reduced, so that the overall chip area is decreased.
In a first aspect, the invention is characterized in that a semiconductor memory device is provided with data amps provided to each output terminal for amplifying the voltage of data read out from a memory cell, outputting the result as a first output data, and outputting a second output data which is generated from this first output data; a data compressing circuit for compressing the first output data from each output terminal, and performing testing to determine whether or not this first output data read out from the memory cell is normal based on the compressed results; a plurality of first lines for outputting each first output data to the data compressing circuit from the data amps; and a second line for connecting and outputting the second output data from the data amps to the data compressing circuit using a wired OR.
In a second aspect, the invention is a semiconductor memory device according to claim 1, characterized in that the data compressing circuit performs a compressing process on a plurality of first output data based on the plurality of first output data and the wired OR output data based on the plurality of the second output data
In a third aspect, the invention is characterized in that, in the semiconductor memory device, in which equivalent data is read into all the memory cells in advance when testing, and the data compressing circuit makes a determination of a correct read out when all of the first output data is the same and all of the second output data is the same when read out, and makes a determination of an incorrect read out when one of the first output data differs from the other data or one of the second output data differs from the other data when read out.
In a fourth aspect, the invention is characterized in that the semiconductor memory device is provided with a transistor in which the data amp outputs a second output data using an open drain.
In a fifth aspect, the invention is characterized in that, in the semiconductor memory device, the second line is formed by connecting transistor drains in parallel.
In a sixth aspect, the invention is characterized in that in the semiconductor memory device, precharge transistors are connected to the second line.
In a seventh aspect, the invention is characterized in that, in the semiconductor memory device, a latch circuit is provided to the second line.
In an eighth aspect, the invention is characterized in the provision to a semiconductor memory device of a data amp for each output terminal for amplifying the voltage of the data read out from the memory cell, outputting the result as a first output data, and outputting a second output data generated from the first output data; a data compressing circuit for compressing the first output data of each output terminal, and performing a test to determine whether or not the first output data read out from the memory cell is normal based on the results of this compression; a plurality of first lines for outputting each first output data to the data compressing circuit from this data amp; and a second line for connecting a plurality of OR circuits which perform OR operations between second output data output from the data amp and second data output from other adjacent data amps, performing OR operations between the result of the preceding OR operation and second output data output from other next adjacent data amps, performing OR operations between the second data of all data amps sequentially, and outputting the result of the operation as third output data to the data compressing circuit.
In a ninth aspect, the invention relates to a semiconductor memory device, characterized in that the data compressing circuit performs data compression of a plurality of first output data, based on a plurality of the first output data and the third output data.